As is known, to read the cells of nonvolatile, and in particular flash, memories, the row to which the cell to be read is connected is so biased as to bring the gate terminal of the cell to the read voltage, and the current flowing through the cell is detected. If the cell is written, its threshold voltage must be higher than the read voltage, so that no current is conducted by the cell. If the cell is erased, its threshold voltage must be such as to let current through. And detecting the current flow provides for discriminating between written and erased cells.
To ensure correct read operation and reliable cycling (multiple cycle operation) of the memory array, certain limits are typically observed in the distribution of the threshold voltages of the cells. More specifically, currently used technologies require that the threshold voltage of the best erased cells be above zero, and the threshold voltage of the worst erased cells be about 2.5 V. The lower limit substantially arises from the need to ensure against read errors caused by depleted cells (cells with a threshold voltage below zero), while the upper limit is due to the intrinsic distribution of the cell threshold voltages according to the fabrication technology used.
Since the read voltage normally coincides with the supply voltage, a supply voltage of over 3 V poses no problems. A problem arises in the case of memories operating at low supply voltages V.sub.CC. In fact, with a supply voltage V.sub.CC of 2.5 V, all the cells with a threshold voltage V.sub.t close to this value conduct little or no current, so that the cell is considered written, thus resulting in a read error.
One solution to the problem consists in boosting the read voltage, i.e., supplying the gate terminal of the cell to be read with a voltage higher than the supply voltage and generated by an appropriate booster stage. At present, two solutions based on this principle are known: continuous and pulsating boost.
In the continuous boost solution, a timed circuit supplied with a clock signal provides for gradually charging a boost capacitor to a voltage higher than the supply voltage. The boost capacitor then provides for maintaining a common (boost) line of the memory at the desired overvoltage. The advantage of this solution lies in the small size of the boost capacitor, due to the overvoltage being reached by means of a series of small increments. But precisely for this reason, initial charging, and hence access to the memory when turned on or on re-entry from standby, is very slow. To eliminate the latter delay, a second smaller boost circuit may be used to keep the boost capacitor charged in standby mode, but only at the expense of increased power consumption.
The pulsating boost solution, on the other hand, employs a very large boost capacitor, which is charged by a single pulse only at predetermined times (upon address switching in read mode, or active switching of the chip enabling signal). While solving the problems of slow access on re-entry from standby (or when the memory is turned on) and increased power consumption in standby mode, the pulsating solution presents other drawbacks of its own, due to the large area required for the capacitor and the necessary drive circuits.